1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and relates particularly to a high voltage detection circuit for detecting high positive and negative voltages input to a semiconductor integrated circuit device.
2. Description of the Prior Art
Flash memory is one type of nonvolatile semiconductor memory device capable of storing data without being continuously supplied with current, a task which is accomplished by holding a charge in the floating gate inside the memory cell at which data is stored. Data is stored by charging or discharging the appropriate floating gate using the Fowler-Nordheim tunnel effect or channel hot electrons to store values of 1 and 0. A voltage that is higher than the operating voltage of the device is generally needed to charge or discharge the floating gate.
FIG. 8 is a simplified circuit diagram of a conventional high voltage detection circuit for detecting a high positive voltage. As shown in FIG. 8 the high voltage detection circuit 200 comprises a current mirror load differential amplifier circuit 201, an n-channel MOSFET (nMOS transistor) 202 for controlling the differential amplifier circuit 201, resistors 204 and 205 for voltage dividing the high positive voltage input from a high voltage input terminal 203, an inverter 206 and a reference voltage generator 207. The high voltage input terminal 203 is grounded through resistors 204 and 205.
Note that the reference voltage Vref generated and output by the reference voltage generator 207 is supplied to one input terminal of the differential amplifier circuit 201. The other input terminal is connected between the resistors 204 and 205, and is supplied thereby with the voltage-divided high positive voltage Vh (voltage Vdiv) input from the high voltage input terminal 203.
The output of the differential amplifier circuit 201 is input to the inverter 206, and the output of the inverter 206 is the output of the high voltage detection circuit 200. The high voltage detection circuit 200 outputs to a high voltage generator 208, which comprises a charge pump circuit and outputs the high positive voltage Vh.
The output of the high voltage generator 208 is supplied to a particular circuit, not shown in the figures, and to the high voltage input terminal 203. A digital signal is supplied to the gate of the nMOS transistor 202. When the nMOS transistor 202 is on, the differential amplifier circuit 201 operates, and when the nMOS transistor 202 is off, the differential amplifier circuit 201 stops operating.
With the high voltage detection circuit 200 thus comprised, the divided voltage Vdiv voltage-divided by the resistors 204 and 205 is EQU Vdiv=Vh.times.Rb/(Ra+Rb)
where Ra is the resistance of resistor 204 and Rb is the resistance of resistor 205.
The differential amplifier circuit 201 compares the divided voltage Vdiv and reference voltage Vref. When Vdiv&lt;Vref, the differential amplifier circuit 201 outputs LOW. The inverter 206 thus outputs HIGH, which causes the high voltage generator 208 to drive the charge pump and step up the high positive voltage Vh. When Vdiv&gt;Vref, the differential amplifier circuit 201 outputs HIGH, the inverter 206 thus outputs LOW, and the high voltage generator 208 stops driving the charge pump. Because Vdiv=Vh.times.Rb/(Ra+Rb), the high voltage detection circuit 200 outputs LOW when Vh.times.Rb/(Ra+Rb)&gt;Vref, i.e., when Vh&gt;Vref.times.(Ra+Rb)/Rb, and can therefore detect whether the high positive voltage Vh is less than or equal to Vref.times.(Ra+Rb)/Rb.
The high voltage detection circuit 200 shown in FIG. 8, however, divides the high positive voltage Vh using two resistors 204 and 205, and therefore can only detect one divided voltage Vdiv. As a result, this high voltage detection circuit 200 obviously cannot detect plural high positive voltage values. This problem is resolved by replacing the one resistor 204 with a series circuit of n (where n is a natural number) resistors R1-Rn and nMOS transistors T1-Tn with a sufficiently small gate parallel connected to the corresponding resistors R1-Tn.
Each of the nMOS transistors T1-Tn is connected to a control circuit 211. The control circuit 211 controls the on/off state of each nMOS transistor T1-Tn to control the total resistance of the series circuit comprising the n resistors R1-Rn. It is therefore possible for the control circuit 211 to control the divided voltage Vdiv, and thereby detect plural high voltage values.
A conventional detection circuit for detecting high negative voltage values is described next with reference to the circuit diagram shown in FIG. 10.
The high voltage detection circuit 220 shown in FIG. 10 comprises a current mirror load differential amplifier circuit 221, a differential sense amplifier 224 comprising an inverter 223 and nMOS transistor 222 for controlling the differential amplifier circuit 221, a level converter 227 comprising p-channel MOSFETs (pMOS transistors) 225 and 226, and nMOS transistors 228, 229, and M1-Mn.
The source is connected to the back-gate terminal in pMOS transistors 225 and 226 and nMOS transistors 229 and M1-Mn to use the back-gate effect preventing variation in the threshold value Vth. pMOS transistor 226 and nMOS transistors 228, 229, and M1-Mn are diode connected.
nMOS transistors 228, 229, and M1-Mn are serially connected to create a series circuit connected between the high voltage input terminal 230 to which the high negative voltage V1 is input and the power supply terminal 231 to which the power supply voltage Vdd is input. The reference voltage VrefA generated by the reference voltage generator 232 is supplied to the gate of nMOS transistor 228. nMOS transistor 229 is connected between nMOS transistor 228 and the power supply terminal 231.
The pMOS transistors 225 and 226 forming the level converter 227 are connected in series. The gate of pMOS transistor 225, which is connected between the power supply terminal 231 and the ground on the power supply terminal side, is connected between nMOS transistors 228 and 229.
One input to the differential amplifier circuit 221 of the differential sense amplifier 224 is connected between the pMOS transistors 225 and 226 of the level converter 227, and the other input is connected to the reference voltage VrefB generated by the reference voltage generator 232. The differential amplifier circuit 221 outputs to the inverter 223, which outputs the output of the high voltage detection circuit 220 to the high voltage generator 233. The high voltage generator 233 comprises a charge pump circuit to generate and output a high negative voltage V1.
The output of the high voltage generator 233 is supplied to a particular circuit, not shown in the figures, and to the high voltage input terminal 230. A digital signal is supplied to the gate of the nMOS transistor 222. When the nMOS transistor 222 is on, the differential amplifier circuit 221 operates, and when the nMOS transistor 222 is off, the differential amplifier circuit 221 stops operating.
The series circuit comprising the diode-connected nMOS transistors M1-Mn and nMOS transistor 228, to the gate of which is input the reference voltage VrefA, passes current according to the voltage difference between the reference voltage VrefA and the high negative voltage V1. This current flows from the diode connected nMOS transistor 229, producing a voltage Va between the source and drain of the nMOS transistor 229. All of the nMOS transistors 228, 229, and M1-Mn have gates of the same size, and the following equation [1] is true when all are on. EQU (VrefA-V1)/(n30 1)=Va [1]
The level converter 227 converts the input voltage Va to a voltage Va referenced to the ground potential, and the differential amplifier circuit 221 compares the voltage Va converted by the level converter 227 with the reference voltage VrefB. As a result, reference voltage VrefB is compared with (VrefA-V1)/(n+1), V1 is compared with {VrefA-(n+1)).times.VrefB}, and high negative voltages can be detected by using a high integer value for n.
The problem with the high positive voltage detection circuit 210 shown in FIG. 9 is that the number of resistors R1-Rn must be increased to adjust the divided voltage Vdiv in fine increments. This increases the number of outputs from the control circuit 211, which increases the size of the circuit. The chip size also grows as the number of resistors increases, and both factors increase device cost.
With the high negative voltage detection circuit 220 shown in FIG. 10 the large number of circuit elements invites a drop in detection precision while also increasing cost and current consumption. This thus also conflicts with the constant desire to reduce current consumption in semiconductor devices.